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Post by VDC 8x2 on Jun 8, 2014 14:23:56 GMT
A store and fetch routine for the vdc to and from main memory. It works in page length chunks.
The page number is stored in .a when you call the routine. The main memory address is stored in $fe-$ff.
On a normal 16k vdc the address space from $1000-$2000 is empty. so I thought why not use it for data storage.
On a 64k vdc the space is a lot more.
could be sorta like a VDCREU.
VDCADR = $D600
VDCDAT = $d601
zpagepnt = $fe ;address of main mem
; .a = VDC256ByteBank
*=$1300
start jmp push
jmp pull
setregs ldy #$12
sty vdcadr
sta vdcdat
iny
sty vdcadr
lda #$00
sta VDCDAT ;set address
tay
lda #$1f
sta vdcadr
rts
push jsr setregs
@loop lda (zpagepnt),y
sta vdcdat
iny
bne @loop
rts
pull jsr setregs
@loop lda vdcdat
sta (zpagepnt),y
iny
bne @loop
rts
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Post by hydrophilic on Jun 9, 2014 19:30:52 GMT
Have you tested this on real hardware? I initially did something like this with BASIC V7.80, but it was so unreliable! Lines would have gaps or random "noise" around them. All due to not checking the "ready bit"! I mean my original version worked fine in VICE, but was just total crap on real hardware. I also tried reducing RAM refresh to the minimum to improved VDC response time; it helped a little, but memory access was still unreliable!
So you always need to check the ready bit before storing reading/writing register $1f. This makes sense to me. Most every other VDC register it does not matter. However, I did discover that the update address high (reg.$12) also must check "ready" to be reliable. For setting update address low (reg.$13), it is not needed.
Here is how I would rewrite it...
setregs ldy #$12
sty vdcadr
- bit vdcadr ;test ready
bpl - ;wait... needed for update address high
sta vdcdat ;set address high
iny
sty vdcadr
lda #$00
;no need to wait for update address low
sta VDCDAT ;set address low
...
push jsr setregs
@loop lda (zpagepnt),y
- bit vdcadr
bpl - ;wait is need to access RAM register
sta vdcdat
...
pull jsr setregs
- bit vdcadr
bpl - ;wait is need to access RAM register
@loop lda vdcdat
sta (zpagepnt),y
...
I'm 100% sure about the update address high, and writing to VDC RAM (the 'push' routine). I'm slightly less confident about reading VDC RAM, because I just don't do it as often. Sometimes, if you can sync your code to the VDC, you can make a dozen or more writes to VDC RAM in a row by only checking the "ready" bit once. Well that optimization would make your simple code a bit more complex, so I haven't tried to show it.
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Post by VDC 8x2 on Jun 10, 2014 17:22:12 GMT
so anything to do with the write register, address or data, have to be synced. okay
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Post by VDC 8x2 on Jun 10, 2014 18:45:57 GMT
The new routine that writes or reads 8 times in a row.
VDCADR = $D600
VDCDAT = $d601
zpagepnt = $fe ;address of main mem
bittube = $fd
; .a = VDC256ByteBank
*=$1300
start jmp push
jmp pull
setregs ldy #$12
sty vdcadr
bit vdcadr
bpl *-3
sta vdcdat
iny
sty vdcadr
lda #$00
sta VDCDAT ;set address
tay
lda #$1f
sta vdcadr
rts
push jsr setregs
@loop1 lda #$01
sta bittube
bit vdcadr
bpl *-3
@loop lda (zpagepnt),y
sta vdcdat
asl bittube
iny
bcc @loop
bne @loop1
rts
pull jsr setregs
@loop1 lda #$01
sta bittube
bit vdcadr
bpl *-3
@loop lda vdcdat
sta (zpagepnt),y
asl bittube
iny
bcc @loop1
bne @loop
rts
The bit is shifted through the tube in 8 steps where on the 8th step it hits the carry flag.
The Y reg is kept current so the bne at the end will still happen after 256th time.
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