Have you tested this on real hardware? I initially did something like this with BASIC V7.80, but it was so unreliable! Lines would have gaps or random "noise" around them. All due to not checking the "ready bit"! I mean my original version worked fine in VICE, but was just total crap on real hardware. I also tried reducing RAM refresh to the minimum to improved VDC response time; it helped a little, but memory access was still unreliable!
So you always need to check the ready bit before storing reading/writing register $1f. This makes sense to me. Most every other VDC register it does not matter. However, I did discover that the update address high (reg.$12) also must check "ready" to be reliable. For setting update address low (reg.$13), it is not needed.
Here is how I would rewrite it...
setregs ldy #$12 sty vdcadr - bit vdcadr ;test ready bpl - ;wait... needed for update address high sta vdcdat ;set address high iny sty vdcadr lda #$00 ;no need to wait for update address low sta VDCDAT ;set address low ... push jsr setregs @loop lda (zpagepnt),y - bit vdcadr bpl - ;wait is need to access RAM register sta vdcdat ... pull jsr setregs - bit vdcadr bpl - ;wait is need to access RAM register @loop lda vdcdat sta (zpagepnt),y ... I'm 100% sure about the update address high, and writing to VDC RAM (the 'push' routine). I'm slightly less confident about reading VDC RAM, because I just don't do it as often. Sometimes, if you can sync your code to the VDC, you can make a dozen or more writes to VDC RAM in a row by only checking the "ready" bit once. Well that optimization would make your simple code a bit more complex, so I haven't tried to show it.