So my plan is to use the free io pin in the 128 and hook it to the write enable. I need to check what the ram does in regards to output/write conflicts but I think it should work.
What I am not sure about is, can I just write to £08000+ while the SRAM has it's write enable high and have the data appear on the correct pins? I wasn't sure if there was any latching of the data pins or address pins that would make the correct signals not appear on the SRAM.
If this is a valid approach I might actually just cut the existing track to that pin on U36 and add a jumper wire on the rear of the PCB as a permanent fix because it shouldn't hurt the use of option roms.
Having 32k of battery backed bootable ram in my 128 will be awesome.
So a little research later and I need a latch and an AND gate. pin 12 from U3 decodes for $d700. That pin will feed the clock of a latch with the input being the R/W line. So if you read d700 it sets the latch output and if you write to d700 it clears the latch output. This latched state is then AND with the live R/W pin and sent to the write enable on the SRAM.
The result being that to enable writing to the SRAM you write to d700, then write to the memory in $8000-$FFFF and it gets written to the SRAM as well as normal ram (ugh). When done read from d700 and it puts the SRAM back into "write protected" state where writes to $8000-$FFFF are not written to the SRAM.
This is the best I can come up with. It preserves the "ROM" state of the U36 chip but allows writes when wanted and doesn't mess anything else up. Only requires 2 more chips and a couple jumper wires. The mod will have no effect on the cartridge port or normal option roms placed in the socket so no need to remover or reverse it.
It's also valid for a normal SRAM chip in that socket just to use as a ram expansion. The 32k could be used like a ramdisk for loading graphics data from disk into before loading the main program into ram. As the data can be read from normally (unlike the VDC ram) you would have a 32k ram upgrade with no crazy read restrictions. Just a slightly awkward write process..
Spent time last night working on the assembly code. I now have an "option rom" in the SRAM that on boot copies the hours and minutes into the CIA ToD register and makes sure the correct 60hz bit is set. I can type go64 and see the time is still there, but sadly my 64 Kernal sets the 50hz flag again. I need to edit the rom Other than that, in 128 mode the ToD is set correctly and everything works. I can add more code to the sram now I know it works.