8x1 vdc mode trick? Nov 5, 2018 12:48:36 GMT
Post by willymanilly on Nov 5, 2018 12:48:36 GMT
The attached tests times the delay instead of waiting for VBLANK to set the character total vertical height back to a number greater than 0. In this case I use a value of 1. All the tests delay 250 scan lines after VBLANK is cleared and character total height is set to 0. This is similar to the method RFO uses except RFO uses CIA timers for hit the correct scanline. Note this test is for PAL c128D with main cpu running at 0.985248 Mhz. NTSC uses a different frequency for it's main cpu so will be out of sync with the VDC clock for this test. It should be relatively simple to update the program to have correct timing for NTSC machines but I do plan on updating the program when I get back from QLD to automatically detect NTSC or PAL and adjust the timing appropriately. I will be using the detection code in my VDC split test program as well.
The only difference between the tests the value in register 6. The value of 249 and 250 for register 6 are to late so the vertical display overflows to the value in register 4. The value of 251 is after 250 so the vertical display is triggered at row 251. RFO use the latter method so the display is at the intended value.
To run the tests it's sys 4864. The screen will go blank and if the VDC memory is loaded with an image it will display assuming the VDC attribute and display latches are set properly. Pressing space will output 2 hex number on the VIC screen. The first number is the approximate total VIC cycles per VDC frame. The second is approximate VIC cycles to VBLANK when the character vertical height is switch back to 1. VDC scanlines can be calculated by the following formula for each result. ((result*2000000)/985248)/127 rounded to nearest whole number.
eg 4048hex = 16456
((16456*2000000)/985248)/127 = 263 VDC scanlines
All the above is modeled in the latest version of Z64K!
vdcntsc.zip (629.84 KB)