|
Post by willymanilly on Nov 5, 2018 12:48:36 GMT
The attached tests times the delay instead of waiting for VBLANK to set the character total vertical height back to a number greater than 0. In this case I use a value of 1. All the tests delay 250 scan lines after VBLANK is cleared and character total height is set to 0. This is similar to the method RFO uses except RFO uses CIA timers for hit the correct scanline. Note this test is for PAL c128D with main cpu running at 0.985248 Mhz. NTSC uses a different frequency for it's main cpu so will be out of sync with the VDC clock for this test. It should be relatively simple to update the program to have correct timing for NTSC machines but I do plan on updating the program when I get back from QLD to automatically detect NTSC or PAL and adjust the timing appropriately. I will be using the detection code in my VDC split test program as well.
The only difference between the tests the value in register 6. The value of 249 and 250 for register 6 are to late so the vertical display overflows to the value in register 4. The value of 251 is after 250 so the vertical display is triggered at row 251. RFO use the latter method so the display is at the intended value.
To run the tests it's sys 4864. The screen will go blank and if the VDC memory is loaded with an image it will display assuming the VDC attribute and display latches are set properly. Pressing space will output 2 hex number on the VIC screen. The first number is the approximate total VIC cycles per VDC frame. The second is approximate VIC cycles to VBLANK when the character vertical height is switch back to 1. VDC scanlines can be calculated by the following formula for each result. ((result*2000000)/985248)/127 rounded to nearest whole number.
eg 4048hex = 16456
((16456*2000000)/985248)/127 = 263 VDC scanlines
All the above is modeled in the latest version of Z64K!
Attachments:vdcntsc.zip (629.84 KB)
|
|
|
Post by tokra on Mar 22, 2019 15:09:06 GMT
Any progress with this? I'm still thinking about improving compatibility of the 480x240 8x1-mode for NTSC/PAL or maybe even create a 480x576 mode if the method you suggested earlier is indeed possible...
Either way: All the VDC-findings you made while creating your emulator should really be compiled and sorted. And your test-programs should go into the VICE-test-program-repository, after maybe some touch-ups.
Anything I can do to help?
BTW: I'm starting to suspect the myth of "every VDC runs at a slightly different speed" might be unjustified. Could it be this is due to register 0 being initialized differently between NTSC/PAL and ROM-revisions? My suspicion is that every VDC runs at the same speed once the registers are set to the same values. Can you think of test-program for this?
|
|
|
Post by willymanilly on Mar 22, 2019 22:03:27 GMT
I've been focused on version 2 of Z64K which is a total rewrite of the emulator so I haven't revisited this in awhile. It would be good to have a proper suite of test programs and it is something I planned on doing when it comes time to fine tune the VDC emulation in the new version of Z64K. I definitely welcome anyone to create a suite of test programs based on the information and source I've already provided and share on the VICE repository. It could be awhile before I get around to it. It would be great to at least see an 8x1 VDC mode mania with improved compatibility using the information already discovered. BTW: I'm starting to suspect the myth of "every VDC runs at a slightly different speed" might be unjustified. Could it be this is due to register 0 being initialized differently between NTSC/PAL and ROM-revisions? My suspicion is that every VDC runs at the same speed once the registers are set to the same values. Yes, totally agree with the above comment. The only thing to consider once all register values are set to the same value is the speed difference between the VICII and VDC when syncing the screens. As you know VIC PAL is 985258 cycles/second and VIC NTSC is 1022727 cycles/second. All static VDC screens should refresh at the same rate. I probably need to review my code but I think the screen refresh info at the start of my VDC split program assumes all VDC's have a 16Mhz dot clock. c-128.freeforums.net/thread/600/vdc-raster-split?page=3.
|
|