I attempted to get an interlaced image working and it seems that the vertical fine adjustment (remainder or total pixel rows divided by row height) needs to be increased by one to look right. Otherwise it looks like even and odd lines are swapped. It doesn't make any sense to me. Has anyone else the same experience?
The VDC chip is very frustrating to use because of the lacking documentation. Just like double pixel mode it is unclear what registers are actually affected by interlace.
Yes, for some reason or other register 5 needs to be increased by one. This is what I found out doing my VDC Mode Mania back then and IIRC by analysing Graphic Booster and the old "64er Sonderheft 29".
I had tried once on my Commodore 1901. With RGB I think it needed one added, when going through the monochome-signal (BAS) I think it required nothing added. So there seems to be no right or wrong way to do it and user-interaction may be required...