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Post by VDC 8x2 on Jun 16, 2014 15:26:21 GMT
What were the post count titles used on the forum?
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Post by VDC 8x2 on Jun 16, 2014 15:11:42 GMT
I would be interested in testing.
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Post by VDC 8x2 on Jun 13, 2014 23:18:25 GMT
Are there any new developments on the ACE 128 os?
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Post by VDC 8x2 on Jun 13, 2014 23:12:49 GMT
The basic loader for gatewayvdc. I changed my mind and put kernal in bank 1 again. with bank 0 for moduals.
5 bank 15 15 poke 47,0:poke 48,192:clr:rem variables to $c000 25 aa = peek (54534):poke 54534, aa or 1:rem turn on 4k shared mem at bottom 35 graphic clr:color 6,1:graphic 5,1:dd = 8 45 poke 3017,1:vv = 3072:poke vv+672,0 55 print:print"gateway to the savage frontier vdc v1.0":rem 06/13/2014 65 bload"linker",p(dec("1000")),b1,u(dd) 75 poke vv+785,3:rem next prog 85 poke vv+786,1:rem disk # 95 sleep 1 105 bload"library",p(dec("2000")),b1,u(dd) 115 poke 2958,dd:rem drive # 125 sleep 1 130 bload"bankjump",p(dec("0ac8")),b0,u(dd) 135 poke 2594,128 145 POKE 808, 112:POKE 792, 98:rem disable run/stop 155 color 6,13 165 poke 2564,192:poke 216,255 rem turn off basic and kernal updates irq 175 fast:bank 1:sys dec("1000")
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Post by VDC 8x2 on Jun 11, 2014 21:03:25 GMT
$D8 GRAPHM has some unused bits. They could be used to indicate color cell size in the future.
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Post by VDC 8x2 on Jun 11, 2014 20:56:42 GMT
Is there a way to overload the bsave and bload commands to save to and from vdc memory?
vdc would most likely be too slow for that.
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Post by VDC 8x2 on Jun 11, 2014 19:12:44 GMT
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Post by VDC 8x2 on Jun 10, 2014 20:29:18 GMT
all fixed. ;-p lol
ty for catching that.
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Post by VDC 8x2 on Jun 10, 2014 18:45:57 GMT
The new routine that writes or reads 8 times in a row.
VDCADR = $D600 VDCDAT = $d601 zpagepnt = $fe ;address of main mem bittube = $fd ; .a = VDC256ByteBank *=$1300 start jmp push jmp pull
setregs ldy #$12 sty vdcadr bit vdcadr bpl *-3 sta vdcdat iny sty vdcadr lda #$00 sta VDCDAT ;set address tay lda #$1f sta vdcadr rts
push jsr setregs @loop1 lda #$01 sta bittube bit vdcadr bpl *-3 @loop lda (zpagepnt),y sta vdcdat asl bittube iny bcc @loop bne @loop1 rts
pull jsr setregs @loop1 lda #$01 sta bittube bit vdcadr bpl *-3 @loop lda vdcdat sta (zpagepnt),y asl bittube iny bcc @loop1 bne @loop rts
The bit is shifted through the tube in 8 steps where on the 8th step it hits the carry flag.
The Y reg is kept current so the bne at the end will still happen after 256th time.
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Post by VDC 8x2 on Jun 10, 2014 17:41:15 GMT
Awsome! Thank you for the code. going to fire it up and test it.
Do you use any new zero page locations for your commands?
What about 8x4 and 8x2 graphic modes?
Where does it store the VDC graphic info in 64k VDC?
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