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Post by Pyrofer on Aug 20, 2019 9:38:52 GMT
"Standard" output from the VDC is 640 visible pixels, 800 active pixel area (borders included) and total 1024 pixels per line (sync/porch included).
My converter has to sample those pixels. So I match the VDC 16mhz dotclock and sample 1024 pixels per line. That gives me a perfect digical copy of the image.
In order to deal with modes where the width varies there are ONLY two options. 1) count the pixels and dynamically adjust the output width 2) sample only 1024 pixels no matter what is shown so you lose the perfect 1:1 capture
These are actually both complex things to do, option 1 requires some complex logic boyond the chips I currently use. Option 2 requires dropping the full frame decode and resyncing on every hsync pulse. Option 2 can be added into the full frame converter, so you should still be able to show most crazy modes but at the expense of clarity. option 1 will require a complete redesign and make the whole thing cost a lot more again, for a very very small use case.
My current thinking is that for the amount those odd modes are used there is no point making an even bigger adaptive circuit and I will try to squeeze option 2 in. That way you can see the picture but there will be some pixel shifting. It think most mode should fit inside the 1024 pixels I capture anyway, so it won't be the end of the world.
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Post by Pyrofer on Aug 20, 2019 8:15:44 GMT
Real hardware it is then!
Mention the custom rom thing to the Z64K dev, he seems very active and would probably help you.
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Post by Pyrofer on Aug 20, 2019 8:13:29 GMT
My issue with a full frame converter is it would be fixed at 1024 pixels wide.
Any screen mode that changes the total pixel width won't work. If it jiggles the width back and forth along the image and averages 1024 per line, you might still get a picture, but if its just 1 pixel off total, the image will not be in sync.
So I guess I still need a line doubler fallback mode to help deal with odd outputs on the VDC.
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Post by Pyrofer on Aug 19, 2019 13:45:17 GMT
Ok. So the scandoubler works. You get a pretty amazing picture, it's rock solid and looks great. I now have a choice. This design is a simple line doubler. It does not work with interlaced images. I have 3 options now,
1) Add a small bit to the design to enable it to show interlaced images and have a switch to fill in scanlines when not showing interlace 2) Redisgn as a full frame converter that takes two whole fields odd and even and converts them into one progressive true VGA de-interlaced image. 3) Leave as is.
There will be cost implications for each. Option one will riase the final price of the board a little. Option 2 doubles the component cost but gives the best output. Lastly, option 3 would be the cheapest final product price.
What are peoples feelings on this?
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Post by Pyrofer on Aug 18, 2019 0:26:52 GMT
Call for help! (NONE NEEDED! IT WAS MY MONITOR!) Ok. So, I had it mostly working except a slight drift, I adjusted my hsync timing and suddenly I get no picture. The monitor detects a signal (at least it doesn't say no signal) but no pixels are displayed. A scope shows that the output is, as far as I can see, perfect.
I have a suspicion it's to do with when the hsync pulse occurs in relation to vsync. I can find no specific data regarding how that should be treated however.Here you can see Vsync (top) and hsync (bottom) i.postimg.cc/h41Dv2Jx/C2-Hsync-out-C1-Vsync.jpgHere is a close up of Hsync (top) and pixel data (bottom). Note that there is no pixel data during the blanking period (this causes blank screen issues) i.postimg.cc/GhMbJ9xm/C2-pixel-data-C1-Hsync-out.jpgHere you can see a Vsync pulse (top) followed by pixel data (bottom), again, no data in the blanking period i.postimg.cc/1XBsdzxM/C2-pixel-data-C1-Vsync.jpgHere is a comparison of the input and output sync pulses. You can see the scandoubled output is exactly in sync with the original 15khz hsync pulses i.postimg.cc/7hwqX2Rf/C2-Hsync-in-C1-Hsync-out.jpgSo, if anybody knows anything about video sync timing, please help! The monitor in question not only doesn't display pixels but even the buttons stop functioning, as if its too busy to respond. It does however remain powered as if it's detecting a signal.
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Post by Pyrofer on Aug 16, 2019 22:48:02 GMT
Tokra, I think I have an old/bugged version of the mode mania as sometimes it crashes or doesn't load images. I will try and get the latest one and redo the image. I have some more samples and thought it looked quite good myself! mirkosoft, the testcard app isn't mine I will ask the guy who wrote it if he doesn't mind me sharing it. (it's just polite). As far as "flicker fixer" it's not. Currently it does not de-interlace the image, the flickering can be quite bad. I have an idea on how to de-interlace and remove the flicker but it requires massive changes to the design and many many more components. As it is, with a non-interlace image there is no flicker In interlace mode. ugh. But it does flicker in VGA instead of PAL.
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Post by Pyrofer on Aug 16, 2019 16:01:48 GMT
Slowly making progress with this dedicated scandoubler hardware. At the moment one of the issues I don't like is you need to hook into the dotclock pin on the VDC (internal wire mod), but I think I can get around that with some pll stuff on the clock on my board. Anyway, Here is the output i.postimg.cc/KvFqF0bV/Scandoubler-Test-Card.jpgThats a photo of an LCD VGA monitor. I tried mode mania and it seems to work nicely, i.postimg.cc/MZQ92hQq/scandoubleroutput.jpgShown with the monitor info box so you can see it's converted to a VGA resolution And one last picture, I took this using an old VGA monitor from back in the 90s i.postimg.cc/DwQbhc2C/Scandoubleron-CRT.jpgAnyway, lots of progress being made.
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Post by Pyrofer on Aug 15, 2019 17:25:57 GMT
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Post by Pyrofer on Aug 10, 2019 23:48:41 GMT
I will be listing just a couple more PAL units at some point soon, if you or others do still want one. After that all our efforts go into the new board. SO these are probably the last two I will sell.
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Post by Pyrofer on Aug 8, 2019 20:55:16 GMT
I think he was referring to the fact that the PAL 128 and NTSC 128 have different default VDC configurations.
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