Post by oziphantom on Dec 26, 2021 6:24:49 GMT
From Lemon... I got into the idea that the C128 could actually do DMA on the VIC half of the cycle while the CPU is in 2mhz mode. Giving you 2Mhz CPU + 2Mhz DMA, only as somebody pointed out you have an issue where the VIC DRAM Refresh still happens and must but followed.
To which the VIC will drop AEC for those cycles, but you don't get AEC you only get BA. Unless Bil made a modified state in the MMU or PLA for it to put AEC on BA while in 2Mhz mode. Given he did design the system to handle and use 2mhz DMA, he might have, or it got forgotten about.
Anybody know what happens to BA during 2Mhz mode?
