The question is; How will the CIA react to having a value poked into one of its data port at every single Phi2 cycle ? Can it take that ?
The SRQ can only signal at Phi2/4 so it could be assumed it takes a few cycles for a poke to the data port register to be reflected on the output. Anyone ever did that before ?
Added edit: The user port requires buying an adapter to access on the Ultimate 64 but the alternative is the datasette port which has the READ, WRITE and SENSE lines tied directly to the IO port of the CPU. They are filtered with RC filters (of 100 Ohms and 470pF) but the cut-off frequency is 3.38MHz so that's no issue at 500kbps. Do you think it could work on that port ?
Last Edit: Sept 26, 2020 21:57:59 GMT by eslapion: Datasette port solution
The CIA data ports should just latch the data pins straight to the output pins, there might be some delay, ~70ns or so, but I would expect it to hit it directly. There is no really internal logic it needs to do with the pins just latch and hold the value. I would expect it to update every clock without issue. The SRQ is different from the DataPorts as it needs to clock out a serial shift so it does need to run an internal FSM.
if you can get the CPU fast enough to handle sorting the data and hitting the pins fast enough sure as you won't be able to use the REU on the CPU data port.