Post by eslapion on Sept 26, 2020 21:41:03 GMT
see
$DF0A: ADDRESS CONTROL REGISTER
Controlls the address counting during DMA.
If an address is fixed, not a memory block but always the same
byte addressed by the base address register is used for DMA.
Bit 7: C64 ADDRESS CONTROL (1 = fix C64 address)
Bit 6: REU ADDRESS CONTROL (1 = fix REU address)
Bits 5..0: unused (normally all set)
So you want to set bit 7 of DF0A to keep the C64 addresses fixed.
That looks right! codebase64.org/doku.php?id=base:reu_registers
Learning something new every day!
The question is; How will the CIA react to having a value poked into one of its data port at every single Phi2 cycle ? Can it take that ?
The SRQ can only signal at Phi2/4 so it could be assumed it takes a few cycles for a poke to the data port register to be reflected on the output. Anyone ever did that before ?
Added edit: The user port requires buying an adapter to access on the Ultimate 64 but the alternative is the datasette port which has the READ, WRITE and SENSE lines tied directly to the IO port of the CPU. They are filtered with RC filters (of 100 Ohms and 470pF) but the cut-off frequency is 3.38MHz so that's no issue at 500kbps. Do you think it could work on that port ?
