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Post by tschak909 on Apr 30, 2018 1:24:32 GMT
I believe after reading the data sheet for the 8563/8 that it should be possible to program the VDC for a 512x512 interlaced monochrome display, provided that 64k of VDC RAM is available. Problem is, I'm not sure of what to send to the VDC registers to pull this off? This is primarily so that I can write a PLATO terminal for my IRATA.ONLINE service, for the 128 that can render without needing to scale down the drawing output. -Thom (Systems operator for IRATA.ONLINE www.irata.online/) |
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Post by mrbombermillzy on Apr 30, 2018 20:51:58 GMT
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Post by tschak909 on May 1, 2018 18:37:23 GMT
Where can I get that 8568 mode status program? -Thom
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Post by mrbombermillzy on May 1, 2018 19:08:12 GMT
Do you mean the one in the photos from my high resolution thread mentioned above?
If so, thats a program that I cobbled together to change the VDC registers quickly without having to type in the peek/pokes 'blind'. It also shows the status of each register, but only the combined byte values, which is ok for most of them anyway. Perhaps I will upgrade this at some point if necessary.
I can probably put in onto the SD2IEC this weekend (from the floppy) if this is what you are after?
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Post by tschak909 on May 1, 2018 19:21:15 GMT
Yup, that would be most helpful. I really want to see if I can take the vdc2 (640x480 interlaced) tgi driver from cc65 and modify it for 512x512, so that I can do a full screen PLATO terminal without needing to scale any pixels. (it's not character based, it needs to be all points addressable, we'll see how fast it winds up being, but I digress.)
-Thom
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Post by mrbombermillzy on May 1, 2018 20:38:11 GMT
OK, I will try my best to get it to you.  I imagine if you are going to use both the VDC bitmapped mode and the C language to drive the display, you may not get ultra fast screen updates. Not sure if this is needed for an old teaching system..? |
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Post by mrbombermillzy on May 1, 2018 21:09:23 GMT
...In the meantime, here is a little code snippet (courtesy of Craig Bruce) which sets up the VDC for 640x491 interlaced monochrome bitmapped mode. Not too far off what you are looking for really. HTH:
.$1329 [a0 00 ] ldy #$00
.$132b [be 4a 13] ldx $134a,y
.$132e [b9 5e 13] lda $135e,y
.$1331 [e0 19 ] cpx #$19
.$1333 [d0 08 ] bne $133d
.$1335 [20 1b 13] jsr $131b ;read VDC register #.X into .A
.$1338 [29 0f ] and #$0f
.$133a [19 5e 13] ora $135e,y
.$133d [20 0f 13] jsr $130f ;write value .A into VDC register #.X
.$1340 [c8 ] iny
.$1341 [c0 14 ] cpy #$14
.$1343 [90 e6 ] bcc $132b
$134a: 00 01 02 04 05 06 07 08 09 18 19 1b 1c 14 15 0c 0d 1a 0c 0d
$135e: 7e 50 66 4c 06 4c 47 03 06 00 80 00 10 a6 e0 00 e0 00 00 48
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Post by tschak909 on May 1, 2018 21:13:55 GMT
Yeah, this data will be coming in at 2400bps or 9600bps, maybe 19200bps via a wifi modem, so it won't need to be ultra fast. I'm hoping that doing it in C will be okay. If you want to see the service I have developed, you can go to www.irata.online/and you can see a demo video in the videos section. -Thom |
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Post by willymanilly on Oct 21, 2018 23:31:47 GMT
I've started work on rs232 support for Z64K and have implemented the protocol in the unreleased version. Without going into too much detail of the basic rs232 protocol I've used, the implementation I've incorporated into Z64K works and fails as expected from the information I have available. I tested with different baud rates with communication between the c64 and a virtual rs232 device. Baud rates higher than 2400 fail with the standard c64 kernal routines. Errors start appearing with baud rate of 2400. Baud rate of 1800 occasionally fails as well. I think this happens on real hardware but I don't have a rs232 adapter to test with. My experience with using BBS software and modems with the c64/c128 is limited so I welcome any suggestions to what I should be testing before releasing this. i.e what packages do BBS servers expect from the c64 etc.
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