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Post by willymanilly on Oct 7, 2018 4:55:41 GMT
During testing of the new busy status flag implementation of the new VDC for Z64K, I ran c128-vdc-emd.prg from the VICE test repository and it fails now. I tested on real hardware and it fails the same way. The results vary but I've attached a typical screenshot. The page count is sometimes $0040.
I haven't got access to the source code but I'm assuming the busy flag is not checked before reading the data therefore the program is reading corrupt data. The mismatch location should vary. This result is the expected behavior if my new model is correct.
I'd be grateful if other people can run the same program on their setup and let me know the result. You should run the program in 40 column mode. Thanks in advance. 
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Post by virtualsky on Oct 7, 2018 5:08:45 GMT
I tried it quickly on my Linux desktop, running VICE emulator (x128 2.4.9) and it seems to run fine. Haven't had the chance to run it on my real C128, but if I can get around to doing it later, I will for you if you think it will help. David.  |
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Post by willymanilly on Oct 7, 2018 6:28:10 GMT
Thanks but yeah, I'm only after results from a real c128. VICE is a great C64 emulator, however it's c128 emulation still needs a lot of work so it is not the best thing to use as a reference for anything c128 related. VICE doesn't emulate the VDC busy status flag properly therefore the c128-vdc-emd.prg test will always pass.
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Post by bjonte on Oct 7, 2018 7:10:24 GMT
My results on 64 kB PAL machine:
Loaded ok, page count = $0040
Testing em_map/em_use/em_commit
Filling 003F
Comparing 0000
Data mismatch in page $0001 at $2EDF
Data is $0101 (should be $0001)
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Post by bjonte on Oct 7, 2018 7:17:02 GMT
My results on 16 kB NTSC machine:
Loaded ok, page count = $0100
Testing em_map/em_use/em_commit
Filling 00FF
Comparing 0000
Data mismatch in page $0001 at $2EDD
Data is $0000 (should be $0001)
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Post by willymanilly on Oct 7, 2018 7:30:19 GMT
Excellent! They are exactly the results I was hoping for. My PAL c128 has either a page count of $0040 or $0100 when I repeat the test. The main thing I wanted to confirm was the test should indeed NOT pass on ALL real c128's so thanks. |
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Post by tokra on Oct 7, 2018 9:50:04 GMT
I can confirm the results on my C128-PAL-64K-VDC-machine. I get the same error at $2edd or somewhere in the vicinity.
Regarding VDC-emulation: I have been contacted by TWO different emulator-programmers regarding this recently, I referred both to you, willymanilly. Has something come out of that? Apparantly the interest for better VDC-emulation is there :-)
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Post by willymanilly on Oct 7, 2018 10:17:04 GMT
Regarding VDC-emulation: I have been contacted by TWO different emulator-programmers regarding this recently, I referred both to you, willymanilly. Has something come out of that? Apparantly the interest for better VDC-emulation is there :-) No, I haven't had anyone contact me. It's probably best they sign up to this forum with any questions so the answers are public for everyone to see. Good to hear there's more interest in better VDC emualtion. Hope that equates to seeing more VDC demos in future. |
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Post by willymanilly on Nov 30, 2019 2:31:02 GMT
As discussed here, apparently the order of writing to the update location VDC registers(18 and 19) seems to matter. Is that behaviour common knowledge? I've seen no mention of this in the c128 programmers reference guide or mapping the c128. Long story short expect data corruption with your VDC programs if you attempt to update VDC register 19 (least significant byte) before updating register 18 (most significant byte). |
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Post by john-atlanta on Jan 16, 2020 4:24:10 GMT
> As discussed here, apparently the order of writing to the update location VDC registers(18 and 19) seems to matter. Is that behaviour common knowledge?
Yes, at one time it was.
=====
Article 59542 of comp.sys.cbm:
Path: news.acns.nwu.edu!newsfeed.acns.nwu.edu!math.ohio-state.edu!howland.erols.net!www.nntp.primenet.com!nntp.primenet.com!mr.net!news.netins.net!usenet
From: phdss@netins.net (Brett Tabke)
Newsgroups: comp.sys.cbm
Subject: Re: 2 VDC questions
Date: Fri, 06 Dec 1996 16:50:10 -0500
=====
- Don't get caught in the WRITEREG lie. With 2 exceptions: you
do not have to wait for update status to become ready while
writing to a register. The first exception is that you can not
be in the middle of a block fill or a block copy (must wait
till it finishes), and two is you can't do consecutive writes
to vdc ram.
If you are say, updating the current VDC ram address
(reg18/19), then don't worry, write to reg 18 and rock out on
19 without checking the status reg.
The exception to the exception:
With the dram refresh high byte at zero, IRQ's off, and the
VDC status register ready, you can write 8 consecutive bytes
to vdc ram without checking the update status! Additionally;
if you are doing other things inbetween the writes to ram
(such as loading a cpu register with the byte to write) you
can usually ignore the update status register entirely!
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