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Post by jmpff3d on Nov 21, 2018 18:11:47 GMT
Z80 Instruction Set and Timings
Table A-3. Z80 Mnemonics and Operations in Alphabetical Order +------------+--------------------+------+---+---+----------------------+ |Mnemonic |Operation |CZPSNH|Len|Tim|Comments | +------------+--------------------+------+---+---+----------------------+ |ADC A,r |A:=A+r+CY |**V*0*| 1 | 4 | r - A,B,C,D,E,H,L | |ADC A,(HL) |A:=A+(HL)+CY | | 1 | 7 | | |ADC A,n |A:=A+n+CY | | 2 | 7 | n - byte (0..FF) | |ADC A,(ii+n)|A:=A+(ii+n)+CY | | 3 |19 |ii - IX,IY | |ADC HL,rr |HL:=HL+rr+CY |**V*0x| 2 |15 |rr - BC,DE,HL,SP | +------------+--------------------+------+---+---+----------------------+ |ADD A,r |A:=A+r |**V*0*| 1 | 4 | | |ADD A,(HL) |A:=A+(HL) | | 1 | 7 | | |ADD A,n |A:=A+n | | 2 | 7 | | |ADD A,(ii+n)|A:=A+(ii+n) | | 3 |19 | | |ADD HL,rr |HL:=HL+rr |*...0x| 1 |11 | | |ADD IX,ry |IX:=IX+px | | 2 |15 |ry - BC,DE,SP,IY | |ADD IY,rx |IY:=IY+py | | 2 |15 |rx - BC,DE,SP,IX | +------------+--------------------+------+---+---+----------------------+ |AND r |A:=A and r |0*P*01| 1 | 4 | | |AND (HL) |A:=A and (HL) | | 1 | 7 | | |AND n |A:=A and n | | 2 | 7 | | |AND (ii+n) |A:=A and (ii+n) | | 3 |19 | | +------------+--------------------+------+---+---+----------------------+ |BIT b,r |Z:=not rb |.*xx01| 2 | 8 | b - bit number (0..7)| |BIT b,(HL) |Z:=not (HL)b | | 2 |12 |xb - bit b of | |BIT b,(ii+n)|Z:=not (ii+n)b | | 4 |20 | location x | +------------+--------------------+------+---+---+----------------------+ |CALL nn |PUSH PC;PC:=nn |......| 3 |17 |nn - word (0..FFFF) | |CALL cc,nn |If cc then CALL nn | | 3 |17 |cc - C,NC,Z,NZ,M,P,PE,| | | else continue | | |10 | PO | +------------+--------------------+------+---+---+----------------------+ |CCF |CY:=not CY |*...0x| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |CP r |A-r |**V*1*| 1 | 4 | | |CP (HL) |A-(HL) | | 1 | 7 | | |CP n |A-n | | 2 | 7 | | |CP (ii+n) |A-(ii+n) | | 3 |19 | | +------------+--------------------+------+---+---+----------------------+ |CPD |A-(HL);dec HL;dec BC|.***1*| 2 |16 |PV=0 if BC=0,else PV=1| +------------+--------------------+------+---+---+----------------------+ |CPDR |Repeat CPD |.***1*| 2 |21 | | | | until Z=1 or BC=0 | | |16 | | +------------+--------------------+------+---+---+----------------------+ |CPI |A-(HL);inc HL;dec BC|.***1*| 2 |16 |PV=0 if BC=0,else PV=1| +------------+--------------------+------+---+---+----------------------+ |CPIR |Repeat CPI |.***1*| 2 |21 | | | | until Z=1 or BC=0 | | |16 | | +------------+--------------------+------+---+---+----------------------+ |CPL |A:=A xor 255 |....11| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |DAA |Decimal adjust Acc. |**P*.*| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |DEC r |r:=r-1 |.*V*1*| 1 | 4 | | |DEC (HL) |(HL):=(HL)-1 | | 1 |11 | | |DEC (ii+n) |(ii+n):=(ii+n)-1 | | 3 |23 | | |DEC rr |rr:=rr-1 |......| 1 | 6 | | |DEC ii |ii:=ii-1 | | 2 |10 | | +------------+--------------------+------+---+---+----------------------+ |DI |IFF:=0 |......| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |DJNZ e |dec B;if B 0 JR e |......| 2 |13 | e - relative address | | | if B=0 continue| | | 8 | | +------------+--------------------+------+---+---+----------------------+ |EI |IFF:=1 |......| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |EX AF,AF' |AF<->AF' |......| 1 | 4 | | |EX DE,HL |DE<->HL | | 1 | 4 | | |EX (SP),HL |(SP)<->HL | | 1 | 4 | | |EX (SP),ii |(SP)<->ii | | 2 |23 | | +------------+--------------------+------+---+---+----------------------+ |EXX |BC<->BC';DE<->DE'; |......| 1 | 4 | | | |HL<->HL' | | | | | +------------+--------------------+------+---+---+----------------------+ |HALT |Halt CPU |......| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |IM 1 |Interrupt mode 1 |......| 2 | 8 | | |IM 2 |Interrupt mode 2 | | | | | |IM 3 |Interrupt mode 3 | | | | | +------------+--------------------+------+---+---+----------------------+ |IN A,(n) |A:=port(n) |......| 2 |11 | | |IN r,(C) |r:=port(C) |.*P*0*| 2 |12 | | |IN ?,(C) |only set flags as |.*P*0*| 2 |12 |can't be entered as a | | | as IN r,(C) does | | | |command;code is ED 70 | +------------+--------------------+------+---+---+----------------------+ |INC r |r:=r+1 |.*V*0*| 1 | 4 | | |INC (HL) |(HL):=(HL)+1 | | 1 |11 | | |INC (ii+n) |(ii+n):=(ii+n)+1 | | 3 |23 | | |INC rr |rr:=rr+1 |......| 1 | 6 | | |INC ii |ii:=ii+1 | | 2 |10 | | +------------+--------------------+------+---+---+----------------------+ |IND |(HL):=port(C); |x*xx1x| 2 |16 |Z=1 if B=0,else Z=0 | | |dec HL;dec B | | | | | +------------+--------------------+------+---+---+----------------------+ |INDR |Repeat IND |x1xx1x| 2 |21 | | | | until B=0 | | |16 | | +------------+--------------------+------+---+---+----------------------+ |INI |(HL):=port(C); |x*xx1x| 2 |16 |Z=1 if B=0,else Z=0 | | |inc HL;dec B | | | | | +------------+--------------------+------+---+---+----------------------+ |INIR |Repeat INI |x1xx1x| 2 |21 | | | | until B=0 | | |16 | | +------------+--------------------+------+---+---+----------------------+ |JP nn |PC:=nn |......| 3 |10 | | |JP cc,nn |If cc then JP nn |......| 3 |10 | | |JP (HL) |PC:=HL | | 1 | 4 | | |JP (ii) |PC:=ii | | 2 | 8 | | +------------+--------------------+------+---+---+----------------------+ |JR e |PC:=PC+e |......| 2 |12 | | |JR cond,e |If cond then JR e | | 2 |12 |cond - C,NC,Z,NZ | | | else NOP | | | 7 | | +------------+--------------------+------+---+---+----------------------+ |LD r,r |r:=r |......| 1 | 4 | | |LD r,(HL) |r:=(HL) | | 1 | 7 | | |LD r,n |r:=n | | 2 | 7 | | |LD r,(ii+n) |r:=(ii+n) | | 3 |19 | | |LD (HL),r |(HL):=r | | 1 | 7 | | |LD (ii+n),r |(ii+n):=r | | 3 |19 | | |LD (HL),n |(HL):=n | | 2 |10 | | |LD (ii+n),n |(ii+n):=n | | 4 |19 | | |LD A,(BC) |A:=(BC) | | 1 | 7 | | |LD A,(DE) |A:=(DE) | | 1 | 7 | | |LD A,(nn) |A:=(nn) | | 3 |13 | | |LD (BC),A |(BC):=A | | 1 | 7 | | |LD (DE),A |(DE):=A | | 1 | 7 | | |LD (nn),A |(nn):=A | | 3 |13 | | |LD A,I |A:=I |.***00| 2 | 9 |PV=IFF | |LD A,R |A:=R | | 2 | 9 |PV=IFF | |LD I,A |I:=A |......| 2 | 9 | | |LD R,A |R:=A | | 2 | 9 | | |LD rr,nn |rr:=nn | | 3 |10 | | |LD ii,nn |ii:=nn | | 4 |14 | | |LD HL,(nn) |HL:=(nn) | | 3 |16 | | |LD rr,(nn) |rr:=(nn) | | 4 |20 | | |LD ii,(nn) |ii:=(nn) | | 4 |20 | | |LD (nn),HL |(nn):=HL | | 3 |16 | | |LD (nn),rr |(nn):=rr | | 4 |20 | | |LD (nn),ii |(nn):=ii | | 4 |20 | | |LD SP,HL |SP:=HL | | 1 | 6 | | |LD SP,ii |SP:=ii | | 1 |10 | | +------------+--------------------+------+---+---+----------------------+ |LDD |(DE):=(HL); |..*.00| 2 |16 |PV=0 if BC=0,else PV=1| | |dec DE,HL,BC | | | | | +------------+--------------------+------+---+---+----------------------+ |LDDR |Repeat LDD |..0.00| 2 |21 | | | | until Z=1 or BC=0 | | |16 | | +------------+--------------------+------+---+---+----------------------+ |LDI |(DE):=(HL); |..*.00| 2 |16 |PV=0 if BC=0,else PV=1| | |inc DE,HL;dec BC | | | | | +------------+--------------------+------+---+---+----------------------+ |LDIR |Repeat LDI |..0.00| 2 |21 | | | | until Z=1 or BC=0 | | |16 | | +------------+--------------------+------+---+---+----------------------+ |NEG |A:=0-A |**V*1*| 2 | 8 | | +------------+--------------------+------+---+---+----------------------+ |NOP |No operation |......| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |OR r |A:=A or r |0*P*00| 1 | 4 | | |OR (HL) |A:=A or (HL) | | 1 | 7 | | |OR n |A:=A or n | | 2 | 7 | | |OR (ii+n) |A:=A or (ii+n) | | 3 |19 | | +------------+--------------------+------+---+---+----------------------+ |OTDR |Repeat OUTD |x1xx1x| 2 |21 | | | | until B=0 | | |16 | | +------------+--------------------+------+---+---+----------------------+ |OTIR |Repeat OUTI |x1xx1x| 2 |21 | | | | until B=0 | | |16 | | +------------+--------------------+------+---+---+----------------------+ |OUT (n),A |port(n):=A |......| 2 |11 | | |OUT (C),r |port(C):=r | | 2 |12 | | +------------+--------------------+------+---+---+----------------------+ |OUTD |port(C):=(HL); |x*xx1x| 2 |16 |Z=1 if B=0,else Z=0 | | |dec HL;dec B | | | | | +------------+--------------------+------+---+---+----------------------+ |OUTI |port(C):=(HL); |x*xx1x| 2 |16 |Z=1 if B=0,else Z=0 | | |inc HL;dec B | | | | | +------------+--------------------+------+---+---+----------------------+ |POP qq |qq:=(SP);SP:=SP+2 |......| 1 |10 |qq - AF,BC,DE,HL | |POP ii |ii:=(SP);SP:=SP+2 | | 2 |14 | | +------------+--------------------+------+---+---+----------------------+ |PUSH qq |SP:=SP-2;(SP):=qq |......| 1 |11 | | |PUSH ii |SP:=SP-2;(SP):=ii | | 2 |15 | | +------------+--------------------+------+---+---+----------------------+ |RES b,r |rb:=0 |......| 2 | 8 | | |RES b,(HL) |(HL)b:=0 | | 2 |15 | | |RES b,(ii+n)|(ii+n)b:=0 | | 4 |23 | | +------------+--------------------+------+---+---+----------------------+ |RET |POP PC |......| 1 |10 | | |RET cc |If cc then RET |......| 1 |11 | | | | else NOP | | | 5 | | +------------+--------------------+------+---+---+----------------------+ |RETI |Return from interr. |......| 2 |14 | | +------------+--------------------+------+---+---+----------------------+ |RETN |Return from NMI |......| 2 |14 | | +------------+--------------------+------+---+---+----------------------+ |RL r |+------->------+ |**P*00| 2 | 8 | | |RL (HL) ||+--+ +-------+| | | 2 |15 | | |RL (ii+n) |++CY+<+7 <-- 0++ | | 4 |23 | | +------------+ +--+ +-------+ +------+---+---+----------------------+ |RLA | |*...00| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |RLC r | +---->----+ |**P*00| 2 | 8 | | |RLC (HL) |+--+ |+-------+| | | 2 |15 | | |RLC (ii+n) ||CY+<++7 <-- 0++ | | 4 |23 | | +------------++--+ +-------+ +------+---+---+----------------------+ |RLCA | |*...00| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |RLD | A +---->---+(HL)|.*P*00| 2 |18 | | | |+---+-+-++---+-+-+ | | | | | | ||7 4|3 0||7 4|3 0| | | | | | | |+---+-+-++++-+-+-+ | | | | | | | +-<-++-<-+ | | | | | +------------+--------------------+------+---+---+----------------------+ |RR r |+------<-------+ |**P*00| 2 | 8 | | |RR (HL) ||+-------+ +--+| | | 2 |15 | | |RR (ii+n) |++7 --> 0+>+CY++ | | 4 |23 | | +------------+ +-------+ +--+ +------+---+---+----------------------+ |RRA | |*...00| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |RRC r |+---<-----+ |**P*00| 2 | 8 | | |RRC (HL) ||+-------+| +--+ | | 2 |15 | | |RRC (ii+n) |++7 --> 0++>+CY| | | 4 |23 | | +------------+ +-------+ +--+ +------+---+---+----------------------+ |RRCA | |*...00| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |RRD | A +---<----+(HL)|.*P*00| 2 |18 | | | |+---+-+-++---+-+-+ | | | | | | ||7 4|3 0||7 4|3 0| | | | | | | |+---+-+-++++-+-+-+ | | | | | | | +->-++->-+ | | | | | +------------+--------------------+------+---+---+----------------------+ |RST adr |CALL adr |......| 1 |11 |adr - byte (000xxx00b)| +------------+--------------------+------+---+---+----------------------+ |SBC A,r |A:=A-r-CY |**V*1*| 1 | 4 | | |SBC A,(HL) |A:=A-(HL)-CY | | 1 | 7 | | |SBC A,n |A:=A-n-CY | | 2 | 7 | | |SBC A,(ii+n)|A:=A-(ii+n)-CY | | 3 |19 | | |SBC HL,rr |HL:=HL-rr-CY |**V*1x| 2 |15 | | +------------+--------------------+------+---+---+----------------------+ |SCF |CY:=1 |1...00| 1 | 4 | | +------------+--------------------+------+---+---+----------------------+ |SET b,r |rb:=1 |......| 2 | 8 | | |SET b,(HL) |(HL)b:=1 | | 2 |15 | | |SET b,(ii+n)|(ii+n)b:=1 | | 4 |23 | | +------------+--------------------+------+---+---+----------------------+ |SLA r |+--+ +-------+ |**P*00| 2 | 8 | | |SLA (HL) ||CY+<+7 <-- 0+<0 | | 2 |15 | | |SLA (ii+n) |+--+ +-------+ | | 4 |23 | | +------------+--------------------+------+---+---+----------------------+ |SRA r | +-------+ +--+ |**P*00| 2 | 8 | | |SRA (HL) |+>+7 --> 0+>+CY| | | 2 |15 | | |SRA (ii+n) |+-+-------+ +--+ | | 4 |23 | | +------------+--------------------+------+---+---+----------------------+ |SRL r | +-------+ +--+ |**P*00| 2 | 8 | | |SRL (HL) | 0>+7 --> 0+>+CY| | | 2 |15 | | |SRL (ii+n) | +-------+ +--+ | | 4 |23 | | +------------+--------------------+------+---+---+----------------------+ |SUB r |A:=A-r |**V*0*| 1 | 4 | | |SUB (HL) |A:=A-(HL) | | 1 | 7 | | |SUB n |A:=A-n | | 2 | 7 | | |SUB (ii+n) |A:=A-(ii+n) | | 3 |19 | | +------------+--------------------+------+---+---+----------------------+ |XOR r |A:=A xor r |0*P*00| 1 | 4 | | |XOR (HL) |A:=A xor (HL) | | 1 | 7 | | |XOR n |A:=A xor n | | 2 | 7 | | |XOR (ii+n) |A:=A xor (ii+n) | | 3 |19 | | +------------+--------------------+------+---+---+----------------------+
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Post by jmpff3d on Nov 21, 2018 18:14:06 GMT
Z80 "undoc op" tangent follows:
From: mgr11@cus.cam.ac.uk (M.G. Rison) Subject: Re: More on DD undocumented opcodes Date: Tue Feb 06 05:51:41 EST 1996 Organization: University of Cambridge, England Lines: 55 This DD discussion has slightly sprawled out of control, so let me summarise my understanding of the situation. Comments, and especially corrections, are welcome! A DD preceding an instruction causes, in general, the following (`main') instruction to be processed as normal, except that: - any access to (HL) gets treated as an access to (IX+d), where d is the (signed) displacement byte after the main instruction opcode - any access to HL gets treated as an access to IX - any access to H gets treated as an access to IXh - any access to L gets treated as an access to IXl If the main instruction does not access any of (HL), HL, H and L, then the DD effectively acts as a NOP. (In addition, a series of DDs and FDs acts as a series of NOPs with the DD/FD actually obeyed being the last one in the series.) There are exceptions to the general rule, however. These are: Main instruction Effect of DD ---------------- ------------ CBxx See below EDxx Ignored (acts as NOP) LD H,(HL) LD H,(IX+d) LD (HL),H LD (IX+d),H LD L,(HL) LD L,(IX+d) LD (HL),L LD (IX+d),L EX DE,HL Ignored (acts as NOP) EXX Ignored (acts as NOP) DDCB sequences always cause the byte following the CB to be taken as a displacement, and always cause an access to (IX+d). If the sequence produces output other than in the flags (i.e. all except BIT), then the result gets placed both into (IX+d) and the register one would normally expect to be altered. For example, DD RLC B causes RLC (IX+d) and copies the result into B too. DD SET 3,A causes SET 3,(IX+d) and copies the result into A. DD BIT 7,E causes BIT 7,(IX+d). (The notation LD B,{RLC (IX+d)} is an inspired one -- I would like to make it clear I do not claim authorship; I think I picked it up from somewhere else.) If this is all common knowledge, I apologise for wasting people's time, and would be grateful for a pointer to such information! [Is this the right place to ask Z80 questions, BTW, or is there a more appropriate newsgroup?] Mark ====================================================================== | rison@hep.phy.cam.ac.uk | Esperanto - lingvo inter-nacia | | rison@vxcern.cern.ch | * Mi estas riisto * | ====================================================================== From: mgr11@cus.cam.ac.uk (M.G. Rison) Newsgroups: comp.os.cpm,comp.sys.sinclair,comp.sys.amstrad.8bit Subject: Z80 F effects Followup-To: comp.os.cpm Date: Mon Feb 19 15:07:06 EST 1996 Organization: University of Cambridge, England Lines: 88 [Note followups.] A while ago I posted (to comp.os.cpm) a summary of my understanding of the undocumented Z80 DD/FD (index) instructions. This was met with deafening silence, but I've been assured that's because it was truly perfect. I've now been encouraged to post a summary of my understanding of effects of all the instructions on the F register. This has holes in it, which I'd be more than happy to see filled. I'd also very much like to know whether the bits which I think I understand are in fact not correct. My Zilog reference is a datasheet from 1982. The 8 bits in the Z80's flag register F are, from b7 to b0: S (sign) Set if the result is negative (most significant bit set) Z (zero) Set if the result is zero F5 Undefined H (half carry) Set if there is a carry/borrow between the low and high nybbles F3 Undefined PV (parity/overflow) Set if the result has even parity (logical operations) Set if signed overflow has occurred (arithmetic operations) N (add/subtract) Set if the operation is a subtraction C (carry) Set if there is a carry/borrow out The table below shows the effect of all instructions on F. ? indicates the eect is not known * indicates the effect is non-standard (see te 0 indicates the flag is reset 1 indicates the flag is set - indicates the flag is not affected S,Z,H,V,P,N and C indicate the effect is as described above r refers to any 8-bit quantity appropriate for that instruction s refers to any 16-bit quantity appropriate for that instruction. Instruction Flags Notes =========== ===== ===== ADD/ADC/SUB/SBC/CP r SZ?H?VNC CP is just SUB with the result thrown away INC/DEC r SZ?H?VN- ADD s --?*?-0C H from MSB ADC/SBC s SZ?*?VNC H from MSB INC/DEC s --?-?--- AND r SZ?1?P00 OR/XOR r SZ?0?P00 RLCA/RLA/RRCA/RRA --?0?-0C RLC/RL/RRC/RR r SZ?0?P0C SLA/SLL/SRA/SRL r SZ?0?P0C SLL is like SLA except b0 gets set RRD/RLD SZ?0?P0- Flags set on result in A BIT n,r *Z?1?*0- PV as Z, S set only if n=7 and b7 of r set CCF --?*?-0C H as old C SCF --?0?-01 CPL --?1?-1- NEG SZ?H?V1C A=0-A (Zaks gets C wrong) DAA SZ???P-? Aaaargh! LD A,R/LD A,I SZ?0?*0- PV as IFF2 [yaze doesn't affect F?] LDI/LDIR/LDD/LDIR --?0?*0- PV set if BC<>0 [Zilog summ says S,Z mod?] CPI/CPIR/CPD/CPDR SZ?H?*1- PV set if BC<>0, other flags from last CP IN r,(C) SZ?0?P0- [Zilog detail says OUT (C),r/(n),A affect F?] INI/INIR/IND/INDR ?*?????? Z set if B=0, port is post-decremented OUTI/OTIR/OUTD/OTDR ?*?????? Z set if B=0, port is pre-decremented All others --?-?--- Except for POP AF and EX AF,AF', of course... Mark ====================================================================== | rison@hep.phy.cam.ac.uk | Esperanto - lingvo inter-nacia | | rison@vxcern.cern.ch | * Mi estas riisto * | ======================================================================
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Post by jmpff3d on Nov 27, 2018 7:32:53 GMT
Undoc Ops, II . . .
----------------------------------------------------------------- ---January 7, 1998 ---Copyright Simeon Cran ---This information pertains to the MYZ80 package version 1.24 ---May be distributed freely as long as the file is not modified in any way. ---No responsibility for the accuracy of this document is accepted by the author. -----------------------------------------------------------------
Undocumented Z80 Instructions =============================
The Z80 chip supports a large number of undocumented Z80 instructions. Registered users of MYZ80 may request inclusion of particular undocumented Z80 instructions not shown to be supported here. Following is a list of the undocumented Z80 instructions supported by this version of MYZ80. Unless noted otherwise, these instructions may be freely used in your Z80 programs.
;******************* Preferred mnemonic: INC IXH OP code: 0DDh,024h Description: Increment the 8 bit byte formed by bits 8 to 15 of IX. NOTES: The operation is the same as any of the INC r insructions
;******************* Preferred mnemonic: INC IXL OP code: 0DDh,02Ch Description: Increment the 8 bit byte formed by bits 0 to 7 of IX. NOTES: The operation is the same as any of the INC r insructions
;******************* Preferred mnemonic: LD C,IXH OP code: 0DDh,04Ch Description: Loads the C register with bits 8 to 15 of the IX register.
;******************* Preferred mnemonic: LD D,IXH OP code: 0DDh,054h Description: Loads the D register with bits 8 to 15 of the IX register.
;******************* Preferred mnemonic: LD D,IXL OP code: 0DDh,055h Description: Loads the D register with bits 0 to 7 of the IX register.
;******************* Preferred mnemonic: LD IXH,C OP code: 0DDh,061h Description: Loads bits 8 to 15 of the IX register with the contents of the C register
;******************* Preferred mnemonic: LD IXH,A OP code: 0DDh,067h Description: Loads bits 8 to 15 of the IX register with the contents of the A register
;******************* Preferred mnemonic: LD IXL,C OP code: 0DDh,069h Description: Loads bits 0 to 7 of the IX register with the contents of the C register
;******************* Preferred mnemonic: LD IXL,D OP code: 0DDh,06Ah Description: Loads bits 0 to 7 of the IX register with the contents of the D register
;******************* Preferred mnemonic: LD IXL,A OP code: 0DDh,06Fh Description: Loads bits 0 to 7 of the IX register with the contents of the A register
;******************* Preferred mnemonic: LD A,IXH OP code: 0DDh,07Ch Description: Loads the A register with bits 8 to 15 of the IX register.
;******************* Preferred mnemonic: LD A,IXL OP code: 0DDh,07Dh Description: Loads the A register with bits 0 to 7 of the IX register.
;******************* Preferred mnemonic: ADC A,IXH OP code: 0DDh,08Ch Description: Add with carry bits 7 to 15 of the IX register to A. NOTES: The operation is the same as any of the ADC A,r instructions.
;******************* Preferred mnemonic: ADC A,IXL OP code: 0DDh,08Dh Description: Add with carry bits 0 to 7 of the IX register to register A. NOTES: The operation is the same as any of the ADC A,r instructions.
;******************* Preferred mnemonic: SBC A,IXH OP code: 0DDh,09Ch Description: Subtract with carry bits 7 to 15 of the IX register from register A. NOTES: The operation is the same as any of the SBC A,r instructions.
;******************* Preferred mnemonic: SBC A,IXL OP code: 0DDh,09Dh Description: Subtract with carry bits 0 to 7 of the IX register from register A. NOTES: The operation is the same as any of the SBC A,r instructions.
;******************* Preferred mnemonic: AND A,IXL OP code: 0DDh,0A5h Description: AND register A with bits 0 to 7 of the IX register. NOTES: The operation is the same as any of the AND A,r instructions.
;******************* Preferred mnemonic: OR A,IXH OP code: 0DDh,0B4h Description: OR register A with bits 8 to 15 of the IX register. NOTES: The operation is the same as any of the OR A,r instructions.
;******************* Preferred mnemonic: OR A,IXL OP code: 0DDh,0B5h Description: OR register A with bits 0 to 7 of the IX register. NOTES: The operation is the same as any of the OR A,r instructions.
;******************* Preferred mnemonic: IN ,(C) OP code: 0EDh,070h Description: Same as IN A,(C) except the A register isn't changed (flags are set as if it was changed). NOTES: This instruction can be used to test and discard the value of a port without destroying any registers.
;******************* Preferred mnemonic: SLAS B OP code: 0CBh,030h Description: Shift Left Arithmetic Special B. Same as SLA B except bit 0 of B is set instead of cleared. NOTES: On Z280 machines this instruction is translated to TSET B causing incompatibility if used in software which must run on Z80 and Z280 machines.
;******************* Preferred mnemonic: SLAS C OP code: 0CBh,031h Description: Shift Left Arithmetic Special C. Same as SLA C except bit 0 of C is set instead of cleared. NOTES: On Z280 machines this instruction is translated to TSET C causing incompatibility if used in software which must run on Z80 and Z280 machines.
;******************* Preferred mnemonic: SLAS D OP code: 0CBh,032h Description: Shift Left Arithmetic Special D. Same as SLA D except bit 0 of D is set instead of cleared. NOTES: On Z280 machines this instruction is translated to TSET D causing incompatibility if used in software which must run on Z80 and Z280 machines.
;******************* Preferred mnemonic: SLAS E OP code: 0CBh,033h Description: Shift Left Arithmetic Special E. Same as SLA E except bit 0 of E is set instead of cleared. NOTES: On Z280 machines this instruction is translated to TSET E causing incompatibility if used in software which must run on Z80 and Z280 machines.
;******************* Preferred mnemonic: SLAS H OP code: 0CBh,034h Description: Shift Left Arithmetic Special H. Same as SLA H except bit 0 of H is set instead of cleared. NOTES: On Z280 machines this instruction is translated to TSET H causing incompatibility if used in software which must run on Z80 and Z280 machines.
;******************* Preferred mnemonic: SLAS L OP code: 0CBh,035h Description: Shift Left Arithmetic Special L. Same as SLA L except bit 0 of L is set instead of cleared. NOTES: On Z280 machines this instruction is translated to TSET L causing incompatibility if used in software which must run on Z80 and Z280 machines.
;******************* Preferred mnemonic: SLAS (HL) OP code: 0CBh,036h Description: Shift Left Arithmetic Special (HL). Same as SLA (HL) except bit 0 of (HL) is set instead of cleared. NOTES: On Z280 machines this instruction is translated to TSET (HL) causing incompatibility if used in software which must run on Z80 and Z280 machines.
;******************* Preferred mnemonic: SLAS A OP code: 0CBh,037h Description: Shift Left Arithmetic Special A. Same as SLA A except bit 0 of A is set instead of cleared. NOTES: On Z280 machines this instruction is translated to TSET A causing incompatibility if used in software which must run on Z80 and Z280 machines. This instruction is typically used to detect Z280 or Z80 processors using the following code:
ld a,40h db 0cbh,37h jp m,Z80 jp p,Z280
;******************* Preferred mnemonic: OP code: 0DDh,0FFh Description: Restart 38h. This works exactly the same as a normal RST 38h instruction except that it is prefixed by the 0DDh byte. The 0DDh byte is ignored. NOTES: In order to single step over instructions, Z80 and 8080 debugging programs attempt to decode an instruction and insert a 0FFh byte after it. The code is then run, causing the instruction to be executed then the 0FFh (a restart 38h which returns control to the debugger). Normally, when a debugger fails to recognise a 2 byte opcode which begins with 0DDh (due to the instruction being for the 64180 or a Z80 instruction unrecognised by an 8080 debugger), it will put the 0FFh straight after the 0DDh. This results in a 0DDh,0FFh instruction which will simply give a RESTART 38h instruction on a real Z80. By making MyZ80 emulate this Z80 behaviour it doesn't do anything particularly useful for the debugging session, but it does prevent MyZ80 from trapping what would otherwise be an illegal instruction.
;*******************
End of File. ------------
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