Post by jmpff3d on Dec 7, 2018 18:27:14 GMT
INSPIRED by the Trinity 2MHz fix ( c-128.freeforums.net/thread/680/trinity-infocom-2mhz-fix ), and thanks to RobertB pointing out the Beyond Zork image archive @ Zimmer's ....... We have a New Thread for a New Infocom fix !
Beyond Zork - ""fixed"", see notes below - csdb.dk/release/?id=172226
The original Beyond Zork does activate 2MHz fast mode, unlike the Trinity game. HOWEVER, Infocom made a mistake with fast mode activation in Beyond Zork. They completely forgot to blank the VIC-II chip. Instead of a properly blanked VIC-II display, Infocom gives us a messy VIC-II screen with bus-data somewhat haphazardly being displayed as the C-128's VIC-IIe is prone to do at 2Mhz. The normal procedure when engaging fast mode is to correctly blank the VIC-II. The kernal function at $77B3 handles this perfectly.
With the VIC-II display blanked, as in this release, the VIC-II doesn't have to steal timing cycles from the processor as it normally does or MAYBE even when stuck in 2MHz. As a result, the C-128 should run about 7 percent faster with the VIC display blanked off.
Beyond Zork - ""fixed"", see notes below - csdb.dk/release/?id=172226
The original Beyond Zork does activate 2MHz fast mode, unlike the Trinity game. HOWEVER, Infocom made a mistake with fast mode activation in Beyond Zork. They completely forgot to blank the VIC-II chip. Instead of a properly blanked VIC-II display, Infocom gives us a messy VIC-II screen with bus-data somewhat haphazardly being displayed as the C-128's VIC-IIe is prone to do at 2Mhz. The normal procedure when engaging fast mode is to correctly blank the VIC-II. The kernal function at $77B3 handles this perfectly.
With the VIC-II display blanked, as in this release, the VIC-II doesn't have to steal timing cycles from the processor as it normally does or MAYBE even when stuck in 2MHz. As a result, the C-128 should run about 7 percent faster with the VIC display blanked off.
Changes from orignal disk image @ autoboot sector/block:
0032 A2 00 LDX #$00
0034 A0 07 LDY #$07
0036 A9 0F LDA #$0F
0038 99 48 DB STA $DB48,Y
003B BD 65 0B LDA $0B65,X ; $0B61 changed to $0B65, reflecting shift in data location after insertion/deletion of code
003E 99 48 07 STA $0748,Y
0041 C8 INY
0042 E8 INX
0043 E0 1A CPX #$1A
0045 90 EF BCC $0036
0047 A5 A1 LDA $A1 ; load jiffyclock byte to set up brief delay via the IRQ-driven jiffyclock
0049 C5 A1 CMP $A1 ; compare byte in A register with zp memory location assigned to relevant jiffyclock byte
004B F0 FC BEQ $0049 ; when the byte in A reg. and byte in memory location no longer match, move on
004D 20 B3 77 JSR $77B3 ; call the FAST MODE routine in kernal (vic-ii blanking, fast mode set, etc.)
0050 20 5F FF JSR $FF5F
0053 A9 05 LDA #$05
0055 8D 06 D5 STA $D506
0058 A9 4E LDA #$4E
005A 8D 00 FF STA $FF00
005D A9 09 LDA #$09
005F 8D 05 D5 STA $D505 ; removed LDA #$01 - STA $D030 which originally came after this STA
0062 4C 00 0C JMP $0C00
$D011 REFERENCE from Mapping the Commodore 128
**
Bit 4: This bit enables or disables the VIC screen display. While the bit is % I, the VIC provides its normal screen output. The bit is initialized to this setting during the IOINIT routine [$EI09]. When the bit is set to %0, the VIC suspends the active portion of the display and provides a solid screen in the border color specified in the register at 53280/$D020. The screen is not erased, just blanked. Any text or graphics will still be intact if the screen is again enabled. With the display blanked, the VIC doesn't have to steal timing cycles from the processor as it normally does. As a result, the 128 actually runs about 7 percent aster with the VIC display off.
