I attempted to get an interlaced image working and it seems that the vertical fine adjustment (remainder or total pixel rows divided by row height) needs to be increased by one to look right. Otherwise it looks like even and odd lines are swapped. It doesn't make any sense to me. Has anyone else the same experience?
The VDC chip is very frustrating to use because of the lacking documentation. Just like double pixel mode it is unclear what registers are actually affected by interlace.
Yes, for some reason or other register 5 needs to be increased by one. This is what I found out doing my VDC Mode Mania back then and IIRC by analysing Graphic Booster and the old "64er Sonderheft 29".
I had tried once on my Commodore 1901. With RGB I think it needed one added, when going through the monochome-signal (BAS) I think it required nothing added. So there seems to be no right or wrong way to do it and user-interaction may be required...
Hi people, I'm stumped how to set interlace 'correctly'. I'm also still learning to do things right, so pardon my ignorance here and there.
I'm using a c128 flat model, 16k VDC, PAL, with Scart to Philips LCD Tv (old HD ready type of early 2000). Also a Samsung TV (to VIC) as secondary test. I've no monitor with cool syncing.
The problem described above states the "TV gets the interlace wrong" problem. So, a TV may switch the Odd/Even fields randomly when trying to synchronize to the provided C128 signal via the Scart.
I understand my TV will simply apply digitization to show the image on the LCD, also creating a progressive image ('deinterlaced', so no 'flimmer'). One can see a possible the incorrect sync very well.
When the interlace bits (reg8, value 3) are switched on the VDC, it might have to restart from the 1st Odd or Even frame. I think the VDC does not do that (perhaps the register is read at the next VBL and applied from there on) Maybe we have to time the update of the register specifically?
I've read on this forum (https://c-128.freeforums.net/thread/67/correct-write-vdc-registers) that one does not need to wait for 'ready' to set a register, only for reading/writing memory via reg31 DA (I found that to be true for my config) But I can imagine additional rules apply when changing syncing behavior of the output.
Result for the TV display I use: I notice the output will be randomly 'inverted' or 'correct' ordering of the PAL-half-frames using the '1986' defaults of VDC and just changing the interlace bit (ignoring the mixup of the output) Switching the 2 modes repeatedly shows I can always get some OK and some NOK syncing.
I can imagine the root of this problem lies in the de-interlacing/digitizing H/W of the TV. For a real old 50Hz TV set the incorrect sync may well be different.
Regarding the topic: fine-adjustment yes/no Reading Tokra's modemania comment I learn: reg4 (VT) 38+1 * 8 (<- reg9-1)= 312 (PAL happy) So for interlace we need 625 lines (right), thus suggesting that 2 * 312 = 624 so we would need 1 fine adjust... but if VDC applies it to both frames then one cannot solve the issue that way. I do see that 'playing' (slow, typing) with the fine (set to 1, 0, 1..) cause the frame capture of the TV to become active and it will sometimes fall into the wrong sync. According to the (great) VIC2e interlace description at (https://sites.google.com/site/h2obsession/CBM/C128/Interlace), and how it works on my TV I also see the 'ordering' of the frames is not controlled. It appears the ordering of 'fields' in PAL may also differ for some source material (Std. definition TV not the same as PAL DV camcorder etc) so one would imagine there is an absolute correct method to set sync for the 2 frames. (see martin.hinner.info/vga/pal.html)
Any idea on the following?: 1. The "fine adjustment", is this applied each frame? 2. Does VDC generate 'Odd' and 'Even' frames when interlace is on? (i.e. half first raster vs. half last raster) 3. Could one 'see' if the Vblank one is in, is the Odd or the Even one? 4. Suggestions on the WHEN to switch the interlace bit? (timing, in a VBlank or, exactly NOT in a VBlank)
I can imagine that perhaps one switches the fine adjust to 1, wait a VBL and switch to 0 so as to 'force' an Even or Off frame (?) Or play with the DEB back and forth to 'simulate' the NTSCevenField/PALoddField