I understood the status bit will go high and low indicating the VDC isn’t blocking ram read or write “All the time” While the REU is sampling the VDC nothing is going on On the processor and The sampling happens faster than any other technique inside the c128 So I thought this REU method should show me exactly what the VDC does as a function of its display-generation without opening up the c128
But I must’ve misunderstood the VDC statusbit, it needing to be written before the status starts acting. (I suppose basic is talking to the VDC before the stash can do anything, making the status bit value n.a.) And in that case I hope someone can point out the pitfalls with the REU and memory setting. Setting the DF00 stuff is easy enough but there is the banking and VIC bank to get right.