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Post by c128old on Aug 31, 2020 15:25:57 GMT
Old system-rom C128 (with the Stash/Fetch bug that keeps bank15 active during transfer):
color0,2;color1,1;graphic1,1
Set REU transfer mode with 'fixed c128' DF0A, reu control = 57098 128=c128 set, 0=count both
D600, vdc status = 54784
bank15;poke57098,128 stash 65535,54784,0,0 bank15;poke57098,0 fetch 8000,8192,0,0
fetch 8000,8192,8000,0
forn=0to8:fetch8000,8192,n*8000,0:sleep1:next
This way I can sample the VDC at 1Mhz, which is not as fast as the C128 can test it. With 64kB per sample I have about 64000/1,000,000 so about 0.06 sample time That is with about 3frames of PAL or NTSC.
The VIC screen shows: Bit7 (UR) always set (huh?) Bit6 (LRF) always set Bit5 (VRT) set in the expected fashion (so, on during v-blank) Bit4 and 3 unset
Weird I expected the Bit7 to go on and off. Any ideas?
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Post by oziphantom on Sept 1, 2020 12:53:03 GMT
maybe the VDC only updates the status when a register is requested. try selecting a register to read/write before the scan.
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Post by c128old on Sept 1, 2020 17:09:46 GMT
I’ll try that, thanks.
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Post by wendling on Sept 4, 2020 10:11:43 GMT
In the book Commodore c128 intern: BASIC is too slow to detect the cleared status byte.
Perhaps the status byte stays cleared only for a short amount of time.
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Post by c128old on Sept 4, 2020 20:35:31 GMT
I understood the status bit will go high and low indicating the VDC isn’t blocking ram read or write “All the time”
While the REU is sampling the VDC nothing is going on On the processor and The sampling happens faster than any other technique inside the c128
So I thought this REU method should show me exactly what the VDC does as a function of its display-generation without opening up the c128
But I must’ve misunderstood the VDC statusbit, it needing to be written before the status starts acting.
(I suppose basic is talking to the VDC before the stash can do anything, making the status bit value n.a.)
And in that case I hope someone can point out the pitfalls with the REU and memory setting. Setting the DF00 stuff is easy enough but there is the banking and VIC bank to get right.
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Post by oziphantom on Sept 5, 2020 6:21:01 GMT
yeah you would need to set up a register and then trigger the REU in Assembly language, BASIC is not going to be fast enough for it.
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