Post by molebrain on Feb 15, 2021 16:21:03 GMT
I'm at odds on where to post this question, but I've recently bought a MCE2VGA FPGA device from Serdashop (MCE2VGA) and I'm having some problems with it. The screen is a bit wavy, as you can see here: youtu.be/7w1KQ1Q0zYs
I thought maybe there was some radio interference or something, but after talking briefly to the programmer, he says it is more than likely a pixel clock issue. He says:
"The pixel clock of the C128 is not exactly 14.3181Mhz like the CGA does. So you need to find out the exact pixel clock and multiply by 8 and change the PLL settings. See 50Mhz * 126 / 55 = 114.5454545 Mhz = 14.31818182
Mhz * 8. This device is pretty dependent on the pixel clock."
I am NOT a FPGA expert at all, but i was able to open up the code (downloaded from here: github.com/lfantoniosi/mce2vga/tree/vga-common-res). Using Quartus, I can see that I can change the pixel clocks from the PLL section of the schematic diagram:
tokra I found a thread about VDC timing from you that I thought would be helpful:
c-128.freeforums.net/thread/439/high-resolution-method?fbclid=IwAR1aev_UYFg6G4xK9K7YCb0vW0VMf_JEek1Sd2ynikWbu_mvf9Ld6so5s98
But I am not sure if this will help me, nor do I understand what values I should plug into this clock settings on the FPGA. Any help from anybody would be greatly appreciated.
-Tony
I thought maybe there was some radio interference or something, but after talking briefly to the programmer, he says it is more than likely a pixel clock issue. He says:
"The pixel clock of the C128 is not exactly 14.3181Mhz like the CGA does. So you need to find out the exact pixel clock and multiply by 8 and change the PLL settings. See 50Mhz * 126 / 55 = 114.5454545 Mhz = 14.31818182
Mhz * 8. This device is pretty dependent on the pixel clock."
I am NOT a FPGA expert at all, but i was able to open up the code (downloaded from here: github.com/lfantoniosi/mce2vga/tree/vga-common-res). Using Quartus, I can see that I can change the pixel clocks from the PLL section of the schematic diagram:
tokra I found a thread about VDC timing from you that I thought would be helpful:
c-128.freeforums.net/thread/439/high-resolution-method?fbclid=IwAR1aev_UYFg6G4xK9K7YCb0vW0VMf_JEek1Sd2ynikWbu_mvf9Ld6so5s98
But I am not sure if this will help me, nor do I understand what values I should plug into this clock settings on the FPGA. Any help from anybody would be greatly appreciated.
-Tony
hehe. I'll keep poking around.
