Post by vmarcus on Jul 11, 2020 3:58:05 GMT
Hello,
although, being new to group, I first tried searching for answers but didn’t quite find what I was looking for.
However, I am starting a Do It Yourself project about how to interface a FPGA board to the Commodore Expansion Cartridge Port.
I am not asking about FPGAs, I am only looking for an additional technical details of the actual Cartridge pins.
I already found a number of articles about build a rom cartridge.
However, here is what I have:
when pin # E (1 MHz clock line) is high and pin #12 (Bus Available) is low, the processor is accessing memory on the bus.
Where pin #5 -R/W enable line is high, then is for a read, otherwise this is for a write.
The address lines A0 thru A15 are specified with pins #F thru Y where the 8 bit data word is specified with pins #15 thu #21.
I am aware that the interface is at 5 volts, but I should also note that the newer CPLD/FPGA are likely to go with 3.3V technology. So 5V input tolerance is a must.
Also as noted, when using the onboard power, I've been informed it’s recommended to use compactors on +5V supply pins #2 & #3.
I’m started starting off with paralleling online ram access, where FPGA is capturing the updated values.
Seems straight forward, upon processor writes, the data word pins are input.
But I’m wondering, upon processor reads, when FPGA data word pins are set for output,
if the supplied data value gets overridden from the internal ram access?
I’m not sure, what happens in this scenario of dual sources?
I figure this likely, isn’t an issue, when the processor detects on external cartridge,
but I’m not sure happens when neither of rom pins (#7, #8, #9, #10, #11, nor #B) are connected.
I plan to use all 16 address lines, directly.
although, being new to group, I first tried searching for answers but didn’t quite find what I was looking for.
However, I am starting a Do It Yourself project about how to interface a FPGA board to the Commodore Expansion Cartridge Port.
I am not asking about FPGAs, I am only looking for an additional technical details of the actual Cartridge pins.
I already found a number of articles about build a rom cartridge.
However, here is what I have:
when pin # E (1 MHz clock line) is high and pin #12 (Bus Available) is low, the processor is accessing memory on the bus.
Where pin #5 -R/W enable line is high, then is for a read, otherwise this is for a write.
The address lines A0 thru A15 are specified with pins #F thru Y where the 8 bit data word is specified with pins #15 thu #21.
I am aware that the interface is at 5 volts, but I should also note that the newer CPLD/FPGA are likely to go with 3.3V technology. So 5V input tolerance is a must.
Also as noted, when using the onboard power, I've been informed it’s recommended to use compactors on +5V supply pins #2 & #3.
I’m started starting off with paralleling online ram access, where FPGA is capturing the updated values.
Seems straight forward, upon processor writes, the data word pins are input.
But I’m wondering, upon processor reads, when FPGA data word pins are set for output,
if the supplied data value gets overridden from the internal ram access?
I’m not sure, what happens in this scenario of dual sources?
I figure this likely, isn’t an issue, when the processor detects on external cartridge,
but I’m not sure happens when neither of rom pins (#7, #8, #9, #10, #11, nor #B) are connected.
I plan to use all 16 address lines, directly.