Post by mirkosoft on Jul 1, 2016 23:38:40 GMT
Hi!
I own Commodore 128DCR with SuperCPU and CP/M Cartridge.
I'm confused in case of Z80 in C128 and Z80 in cartridge.
Z80 in cartridge has shifted addressing that what 8502 see as $0000-$FFFF Z80 sees as $1000-$FFFF...$0000-$0FFF - there is shift $1000 bytes.
Problem is not addressing but I'm confused by reason:
Ok, Commodore 64 and Commodore 128 have the same I/O port
So, ok reason for addressing shift of external Z80 we know, but how works C128's internal Z80?
It has not addressing shift and reset vector is same - both are Z80 - or I mean wrong?
When C128 can handle Z80 reset vector and 8502 I/O - How it works?
Or is possible to set external Z80 to state when disables addressing shift?
Since I'm working with Z80 and CP/M I found many new things - in all cases: internal and external Z80 RAM dump I have, I'm ready to create CP/M 2.2 RAM dump and CP/M 3.0 RAM dump (in 3.0 want to find also CP/M's Easter Egg), I mean that DOS/65 needs not RAM dump, but maybe later. CP/M many times uses Kernal65 for tasks by switching CPU - it makes more free space for CP/M. Dumps will publish.
If anyone has any knowledge about these things, please reply. I want to uncover Z80 mystery.
Miro
I own Commodore 128DCR with SuperCPU and CP/M Cartridge.
I'm confused in case of Z80 in C128 and Z80 in cartridge.
Z80 in cartridge has shifted addressing that what 8502 see as $0000-$FFFF Z80 sees as $1000-$FFFF...$0000-$0FFF - there is shift $1000 bytes.
Problem is not addressing but I'm confused by reason:
Note the $1000 term added to adresses, recreating the 74LS283 adder included in the CP/M cartridge
for address-space shift. This is so because of the conflict betwheen 6510's I/O port and Z80's reset vector, both located at $0000
for address-space shift. This is so because of the conflict betwheen 6510's I/O port and Z80's reset vector, both located at $0000
Ok, Commodore 64 and Commodore 128 have the same I/O port
address C64 and C128
$0000 CPU on-chip I/O port data direction register
$0001 CPU on-chip I/O port data registerSo, ok reason for addressing shift of external Z80 we know, but how works C128's internal Z80?
It has not addressing shift and reset vector is same - both are Z80 - or I mean wrong?
When C128 can handle Z80 reset vector and 8502 I/O - How it works?
Or is possible to set external Z80 to state when disables addressing shift?
Since I'm working with Z80 and CP/M I found many new things - in all cases: internal and external Z80 RAM dump I have, I'm ready to create CP/M 2.2 RAM dump and CP/M 3.0 RAM dump (in 3.0 want to find also CP/M's Easter Egg), I mean that DOS/65 needs not RAM dump, but maybe later. CP/M many times uses Kernal65 for tasks by switching CPU - it makes more free space for CP/M. Dumps will publish.
If anyone has any knowledge about these things, please reply. I want to uncover Z80 mystery.
Miro
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