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Post by eslapion on Apr 27, 2021 6:11:30 GMT
I have more than 100 units in stock!
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Post by eslapion on Jan 29, 2021 5:04:20 GMT
I, ah, did a worse-than-usual job of framing that question, didn't I? I'm sorry. Yes, you correctly deduced what I was trying to ask -- I wanted to know how the board's electrical loading compared against the older construction methods involving, I don't know, a big array of 4116s or whatever else someone had available. I _reeeeally_ didn't intend for it to sound like a snotty request for unpaid design review services. *wince* But yes, the usual thing for the 256K mod is to just add two more flat DRAM banks of 64KiB each. Expansions beyond that involve either trying to guess how the C128's native 1-meg MMU design was _intended_ to be fully realized, or simply ignoring it entirely -- kludging in a PET-style block-swapping scheme instead, controlled through an extra 6522-type peripheral chip with I/O port(s). I'm fairly sure that one design I saw, years ago, actually combined both approaches -- three quarters of the MMU banks were simply 64K blocks of RAM, while each of the remainder were 64K arrays of smaller, independently-mapped blocks. (I can't recall, at this point, whether those were mapped in 4K at a time or 16K at a time. I suppose it doesn't actually matter at this point.) I had no idea your real question revolved around the amount of power used. I just thought it would be relevant to mention that the amount of power used is not at issue if you want to have multiple Saruman-128 in a single C128. A Saruman-128 module consumes about half the power of a single one 4164 DRAM IC and there are 16 of these in a standard C-128. BTW, the 4116 (16k x1) is not used in the C128. A pair of 4416 (16k x4) are used with the VDC and 16 4164 (64k x1) are used for the main RAM. In the C128Dcr, four 4464 (64k x4) are used for main RAM and two more are used for the VDC which has 64kBytes instead of 16. I reeeealy didn't see this as a snotty request but as a technical question which is missing a few important details. I answered the portion I could. I think this can help... www.cubic.org/~doj/c64/mapping128.pdfThe schematics suggested here has the effect of adding new RAMCAS lines which each correspond to 64k of extra RAM. www.zimmers.net/anonftp/pub/cbm/documents/projects/memory/c128/1028/1028.htmlFollowing this plan and using 3 extra Saruman-128 modules on top of the one which replaces the initial 16 DRAM ICs, you should be able to push your C128 to a total of 512k of RAM.
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Post by eslapion on Jan 24, 2021 23:04:36 GMT
It's impossible to satisfy your curiosity not knowing exactly how the extra banks are added.
Saruman-128 is designed to behave like a group of DRAM ICs covering two banks of 64k x8 (equivalent to 16 DRAM ICs of 64k x1 or 4 DRAM ICs of 64k x4) so it should work as replacement for pretty much anything that uses this type of memory chip in the same way.
"If one of these boards is present instead of a huge array of DIP-chip DRAMs, would adding a second copy of the board work as desired?" - You don't give any plan so it's impossible to say yes or no for sure but I would be tempted to say it would considering the extra banks normally use more of the same type of RAM chips. In theory, it's possible to install up to 4 Saruman-128 modules in a C128 and that would still use less power than the real DRAM ICs and you'd get 8 banks.
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Post by eslapion on Dec 8, 2020 6:21:21 GMT
Now AVAILABLE! Order here! Shipping to the U.S. is 8$US. Shipping to Europe is 8 Euros. Shipping to Australia is 10$US.
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Post by eslapion on Dec 3, 2020 1:57:29 GMT
Ray Carlsen indicates he tested the product and he is very satisfied with it.
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Post by eslapion on Dec 1, 2020 2:47:14 GMT
Nicely done, but why? What circumstance could prompt total replacement of my 128's system RAM? I'm totally lost as to the use case. A lot of C128 are fitted with MT (Micron Technology) DRAM chips which fail easily. They also consume a lot of power and 4164 DRAM ICs and are getting harder to come by as they are out of production for more than 20 years now. This single replacement module will do the job of all 16 DRAM ICs using modern static RAM which consume less than 2% the amount of power used by the original 16 4164 DRAM ICs. Less heat, less stress on the power supply and much less likely to fail. Also a solution to the VSP bug, as mentioned by Tokra.
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Post by eslapion on Nov 29, 2020 6:54:14 GMT
Replace all 16 DRAM ICs of the C128 with a single small module for just 15$ or 13 Euros. Saruman-128 prototype installed and working.Coming soon!
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Post by eslapion on Nov 29, 2020 6:50:30 GMT
Saruman-VDC is still available directly from me or through Retroleum in the United Kingdom and Protovision or Polyplay in Germany.
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Post by eslapion on Sept 26, 2020 21:41:03 GMT
There are demos where they change $d020 per clock see $DF0A: ADDRESS CONTROL REGISTER Controlls the address counting during DMA. If an address is fixed, not a memory block but always the same byte addressed by the base address register is used for DMA. Bit 7: C64 ADDRESS CONTROL (1 = fix C64 address) Bit 6: REU ADDRESS CONTROL (1 = fix REU address) Bits 5..0: unused (normally all set) So you want to set bit 7 of DF0A to keep the C64 addresses fixed. That looks right! codebase64.org/doku.php?id=base:reu_registersLearning something new every day! The question is; How will the CIA react to having a value poked into one of its data port at every single Phi2 cycle ? Can it take that ? The SRQ can only signal at Phi2/4 so it could be assumed it takes a few cycles for a poke to the data port register to be reflected on the output. Anyone ever did that before ? Added edit: The user port requires buying an adapter to access on the Ultimate 64 but the alternative is the datasette port which has the READ, WRITE and SENSE lines tied directly to the IO port of the CPU. They are filtered with RC filters (of 100 Ohms and 470pF) but the cut-off frequency is 3.38MHz so that's no issue at 500kbps. Do you think it could work on that port ?
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Post by eslapion on Sept 26, 2020 13:45:30 GMT
wire the SRQ and CLK line up to a data port pin on the user port. Simple cable adapter to make. Then convert each byte into a bit value, and add the clock value toggle write it to the REU twice. Then set the REU to write to a fixed location, set it to the CIA Data Port and then start the transfer. This way you will get the data output at clock/2. That sure seems like a potent trick. The REU is unaffected by the need to perform instructions; it will just dump its content directly to the CIA's data port at the maximum speed of the bus. On a C64, disable the display when this happens and you don't even have to worry about the badlines stealing cycles. Even the refresh cycles occur during the VIC-IIs half cycles. Could you have a small example piece of code ? Added edit: There seems to be a serious problem with your suggestion; the REU's controller is designed to transfer data to/from a series of consecutive addresses in the C64/C128 and the REU's RAM. You set the start address in the C64/C128 RAM, the start address in the REU's RAM, the number of bytes to transfer and finally the direction of the transfer. It's impossible to tell the REU to transfer a series of values to one single (fixed) address.
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