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Post by molebrain on Feb 16, 2021 14:48:58 GMT
Oh wow! I think it is working! I changed the settings of the first PLL2 clk0 and clk3 and there are no waves!!! Screen looks slightly too wide for my screen, but man, it's getting there!!! wooo! THANKS!
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Post by molebrain on Feb 16, 2021 12:52:36 GMT
That would mean X=256 and Y=100 which can be shortened to X=64 and Y=25. So try to enter clock multiplication factor 256 and clock division factor 100 and see what happens. If everything goes up in smoke don't blame me :-) LOL, I will try this out. Hmm...getting frequency out of range on my monitor. I guess that didn't work. Although it may be user error. I'm not sure if/where all the places I need to change these values. This think has 2 PLLs each with multiple clock parameter sections. I'll have to do a little more research. I did get some information from Bil Herd when I asked him what the exact pixel clock is for the C-128, he said that 8.18mhz is my memory, derived from 14.318mhz. Does this change the equation? Thanks everybody for your help.
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Post by molebrain on Feb 16, 2021 4:07:10 GMT
Basically you need to solve this equation 50 * X / Y = 128 ( for a dead on 16Mhz clock if that is what we need) Then you put X where the 16257 is, and you put Y where the 6250 is. oK! I'm not really good at math. HEHE. Any suggestions?
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Post by molebrain on Feb 15, 2021 19:57:59 GMT
Thanks for responding! I am using NTSC model. I figured I'd ask if you or anybody could make heads or tails of it hehe. I'll keep poking around.
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Post by molebrain on Feb 15, 2021 16:21:03 GMT
I'm at odds on where to post this question, but I've recently bought a MCE2VGA FPGA device from Serdashop ( MCE2VGA) and I'm having some problems with it. The screen is a bit wavy, as you can see here: youtu.be/7w1KQ1Q0zYsI thought maybe there was some radio interference or something, but after talking briefly to the programmer, he says it is more than likely a pixel clock issue. He says: "The pixel clock of the C128 is not exactly 14.3181Mhz like the CGA does. So you need to find out the exact pixel clock and multiply by 8 and change the PLL settings. See 50Mhz * 126 / 55 = 114.5454545 Mhz = 14.31818182 Mhz * 8. This device is pretty dependent on the pixel clock."
I am NOT a FPGA expert at all, but i was able to open up the code (downloaded from here: github.com/lfantoniosi/mce2vga/tree/vga-common-res). Using Quartus, I can see that I can change the pixel clocks from the PLL section of the schematic diagram: tokra I found a thread about VDC timing from you that I thought would be helpful: c-128.freeforums.net/thread/439/high-resolution-method?fbclid=IwAR1aev_UYFg6G4xK9K7YCb0vW0VMf_JEek1Sd2ynikWbu_mvf9Ld6so5s98But I am not sure if this will help me, nor do I understand what values I should plug into this clock settings on the FPGA. Any help from anybody would be greatly appreciated. -Tony
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Post by molebrain on Oct 24, 2018 15:36:38 GMT
Hey, this is great. Looking forward to taking a peek at it!
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Post by molebrain on May 17, 2018 15:21:25 GMT
oh yes! thanks Pyrofer. I thought I remembered seeing that before. awesome!
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Post by molebrain on May 17, 2018 14:05:57 GMT
I was just wondering if there was a list of LCD monitors that are 15khz capable, and if so, what are they? I'm looking to get rid of an extra step of using an upscaler for my video output Thanks! -Tony
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Post by molebrain on May 11, 2018 18:14:09 GMT
Woo! Thanks Robert...not only for this, but for letting me know about that Facebook group.
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Post by molebrain on May 4, 2018 20:02:31 GMT
So, what specifically are you asking for us to do? Just curious.
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